Broadly speaking, there are three possible configuration examples.

1. Configured with Hard IP using Stratix IV GX device (1 chip)
Using hard blocks inside the device saves resources and reduces power consumption.
It also complies with Gen 1 & Gen 2 standards.
 
2. Configured using devices with built-in transceivers such as Stratix II GX and Arria GX (1 chip)
x1, x4, x8 lanes of PCI-Express using transceiver blocks and Soft IPs embedded in FPGA
can be configured.

3. Configuration using Cyclone III + external PHY (2 chips)
The FPGA and external PHY are connected using an interface called PIPE.
By separating the upper layer and the PHY layer, the PHY layer can be realized with an external chip (PHY chip), and a low-cost FPGA can be used.
can be used.