I assigned the clock input to the GCLK pin on my MAX II device. Depending on the specification, this clock input may be left open. I would like to make sure that there is no problem even if it is open, but is there any way to do it?

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I assigned the clock input to the GCLK pin in the MAX II device. By design, this clock input may be left open. I would like to make it work even if it is open.Is there any way to do this?

Clock/PLL

The GCLK pin of MAX II devices has a Weak Pull-Up Resistor function,
By using this function, it is possible to protect when open.

The settings are shown below.
1. From the Quartus II menu, select Assignments ⇒ Assignment Editor
2. For the corresponding clock pin,
・ Register the corresponding clock pin name in the To column
・ Set Weak Pull-Up Resistor in the Assignment Name field
- Set Value to "ON"
- Set Enable to "Yes"
3. Compile

Please check the compilation report to see if the settings have been reflected.
The confirmation method is shown below.
1. From the Quartus II menu, click Processing ⇒ Compilation Report ⇒ Fitter ⇒ Input Pins.
2. Check if the Waek Pull Up column for the corresponding GCLK pin is "On".

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