On-chip termination resistors in the transceiver channels are calibrated in the calibration block.
This block ensures that process, voltage, and temperature variations do not affect the termination resistance value.

The termination resistor calibration circuitry in the calibration block requires a calibration clock and cal_blk_clk for clocking is generated when instantiating the ALTGX block on the MwgaWizard Plug-In manager.

The termination resistor calibration block can also be shared when there are multiple transceiver block (ALTGX) instances on the design.

The cal_blk_clk has a frequency range of 10 to 125 MHz and if a clock in this range is not available, a divider circuit should be used to generate an available clock.

If the quality of the calibration clock is not an issue, local routing of the FPGA is sufficient for routing the calibration clock.

If there are multiple ALTGX instances in the device and they are related, the cal_blk_clk ports of all instances must be connected to a common clock.

For details, please search for the keyword "cal_blk_clk" in the Arria II GX Device handbook at the URL link below.
  https://www.altera.co.jp/ja_JP/pdfs/literature/hb/arria-ii-gx/arria-ii-gx_handbook.pdf