Please check the following reasons why the configuration is not completed.

1. Has the Flash-ROM you are using been reset correctly?
⇒ After the power supply stabilizes, the PFL must operate after resetting the Flash-ROM correctly.
If the Flash-ROM is not properly reset, the Flash-ROM becomes unstable and
The phenomenon of repeating the configuration has been confirmed.

2. The CONF_DONE signal has an external 10KΩ pull-up when configuring multiple FPGAs.
In such a case, the CONF_DONE signal may be too dull and the PFL may malfunction.
Again there is the possibility of repeating the configuration.
⇒ As a workaround, for the I/O pin of the MAX II device to which the CONF_DONE signal is connected,
Make Schmitt trigger settings.

Set the I/O Standard to "3.3V Schmitt Trigger Input" in the Assignment Editor,
It is reflected by compiling.

☆ Related materials
- Getting Started with Quartus II - Using the Assignment Editor