One way to reduce I/O timing variation is to use I/O element registers.

The option to use the I/O element register is set for the desired pin through the Assignment Editor (Assignments menu). Devices that support I/O element registers are the Stratix series, Cyclone series, Arria series, APEX series, and FLEX series (excluding FLEX 6000).

・ tsu ⇒ set for data input pin
Option name Fast Input Register
・ tco ⇒ set for data output pin
Option name Fast Output Register

For how to operate the setting, refer to "Setting the IOE register" in the Elsena document "Quartus II Getting Started Guide - Frequently Used Logic Option Setting Method (Individual Setting)".
 
As a design configuration, the following specifications cannot realize I/O element registers. Please be careful.
• Contains combinatorial circuitry between registers and I/O pins.
・ The signal of one input pin is Fan-Outed to two or more registers.
(* Depending on the design, the compiler may automatically merge multiple registers. In that case,
may apply I/O element registers. )
・ The output signal of one last-stage register is Fan-Outed to two or more output pins.
(* Depending on the design, the compiler may automatically insert duplicate registers. In that case,
I/O element registers may be adapted. )