Intel: In order to perform LogicLock from the bottom up, lower level design files are compiled. Because the number of input/output signals (ports) in the lower layer design exceeds the number of pins of the target device, a fitting error will occur and compilation will not be possible.

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Intel: Compiling lower level design files to do LogicLock from the bottom up. Since there are many I/O signals (ports) in the lower layer design and the number of pins of the target device is exceeded, a fitting error occurs and compilation cannot be performed.

Quartus Prime

This can be avoided by specifying virtual pins for the I/O ports in the lower layer design that eventually become intermediate signals in the circuit. I/O ports designated as virtual pins are mapped to the internal logic of the target device.

A virtual pin is specified by a Quartus II option.

In the Assignment Editor, set the "Virtual Pin" option for the desired pin.

For details, refer to "Virtual Pin Settings" in the document "Quartus II Getting Started Guide - How to Set Commonly Used Logic Options (Individual Settings)".

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