The number of clock systems that can be output from one PLL varies depending on the device family. The number of clock output systems for each device is as follows.
For details, please refer to the Device Handbook of each device.
 
Stratix IV
- Top/Bottom PLL : Up to 10 internal clock outputs, of which up to 6 external clock outputs
(using PLL_<#>_CLKOUT pins)
- Left/Right PLL : Up to 7 internal clock outputs, of which up to 2 external clock outputs
(using PLL_<#>_CLKOUT pins)
Document Clock Networks and PLLs in Stratix IV Devices
      https://www.altera.com/en_US/pdfs/literature/hb/stratix-iv/stx4_siv51005.pdf
 
Stratix III
- Top/Bottom PLL : Up to 10 internal clock outputs, of which up to 6 external clock outputs
(using PLL_<#>_CLKOUT pins)
- Left/Right PLL : Up to 7 internal clock outputs, of which up to 2 external clock outputs
(using PLL_<#>_CLKOUT pins)
Document Clock Networks & PLLs in Stratix III Devices
      https://www.altera.com/en_US/pdfs/literature/hb/stx3/stx3_siii51006.pdf
 
Stratix II
- Enhanced PLL: Up to 6 internal clock outputs, of which up to 6 external clock outputs
(using the PLL#_OUT pin)
- Fast PLL: Up to 4 lines as internal clock output
Documentation PLLs in Stratix II and Stratix II GX Devices
      https://www.altera.com/en_US/pdfs/literature/hb/stx2/stx2_sii52001.pdf

Stratix
- Enhanced PLL: up to 6 internal clock outputs, up to 4 external clock outputs
(using the PLL#_OUT pin
- Fast PLL: Up to 3 channels as internal clock output
Document General-Purpose PLLs in Stratix & Stratix GX Devices
      https://www.altera.com/en_US/pdfs/literature/hb/stx/ch_1_vol_2.pdf
 
Cyclone III
- Up to 5 internal clock outputs, including 1 external clock output (c0 port only)
(using the PLL#_CLKOUT pin)
Document Clock Networks and PLLs in Cyclone III Devices
     https://www.altera.com/en_US/pdfs/literature/hb/cyc3/cyc3_ciii51006.pdf
 
Cyclone II
- Up to 3 internal clock outputs, 1 of which is an external clock output
(using the PLL#_OUT pin)
Documentation PLLs in Cyclone II Devices
      https://www.altera.com/en_US/pdfs/literature/hb/cyc2/cyc2_cii51007.pdf
 
Cyclone
- Up to 2 internal clock outputs and 1 external clock output
(using the PLL_OUT pin)
Document Using PLLs in Cyclone Devices
      https://www.altera.com/en_US/pdfs/literature/hb/cyc/cyc_c51006.pdf