Narrow down by specifying conditions
There are currently 4292 hits.
Intel: Are there any restrictions on the placement of clock pins input to the PLL?
The PLL imposes clock pin limits to preserve jitter characteristics.
For example, in the case of Stratix IV, the connection relationship between the PLL and the clock pin can be found from the following document.
Stratix IV Device Handbook, Volume 1, Chapter 5, Clock Networks and PLLs in Stratix IV Devices (PDF file automatically downloads)
=> Table5-4.
Similarly for Cyclone IV see the following resources:
Cyclone IV Device Handbook, Volume 1, Chapter 5, Clock Networks and PLLs in Cyclone IV Devices (PDF file automatically downloads)
=> Figure 5-1 to Figure 5-3.
Experienced FAE
Free consultation is available.
From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.