Category: Quartus® Prime
Tools: Quartus® Prime
device:-


Clocks generated by the PLL also require clock constraints.
Clock constraints are also possible with the create_generate_clock command, but any changes to the PLL parameters will also require modifications to the corresponding part of the .sdc file.
 
On the other hand, the derive_pll_clocks command reads the PLL information (parameters) created in the IP Catalog of Quartus® Prime and automatically sets the output frequency of the PLL.
Therefore, there is no need to modify the SDC file even if the PLL parameters are modified.
This command is a very useful command because it allows you to easily set up the PLL.
 
However, since this command is an SDC command for Intel® FPGA only, it cannot be read by other companies' tools that can use SDC.
 
Intel converts the information set in derive_pll_clocks to derive_pll_clocks ⇒ create_generate_clock by adding the write_sdc -expand option when saving the SDC file so that it can be read by other companies' timing analysis tools.