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Intel: What is the PLL Operation Mode used in the generated design when configuring the LVDS I/F with the ALTLVDS Megafunction?
There are different modes for the Tx (transmit) and Rx (receive) sides.
Tx side: Normal mode is used to maintain the phase relationship between the clock and data in the internal register.
Rx side: Source-Synchronous Mode is used to maintain the phase relationship between clock and data in the IOE part.
You can check what mode is actually set from the compile report.
Confirmation method
Select Compilation Report ⇒ Fitter ⇒ Resource Section ⇒ PLL Summary
Check the PLL mode section
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