You can apply constraints in the Assignment Editor.
 
The setting method for each format is shown below.

■ Constraint methods for primitives
・In the case of circuit diagram format
Right-click on the primitive you want to constrain from the bdf ⇒ Locate ⇒ Select Locate in Assignment Editor
Assignment Editor will start, so set arbitrary constraints from the Assignment Name field
・For VHDL/Verilog HDL
After executing logic synthesis, select Tools ⇒ Netlist Viewers ⇒ RTL Viewer
Right click on the primitive you want to constrain and select Locate ⇒ Locate in Assignment Editor
Assignment Editor will start, so set arbitrary constraints from the Assignment Name field
 
■ Constraint method for design files
After running Analysis & Elaboration, select the Hierarchy tab in the Project Navigator window to see the
The design files that are included are displayed. (Displayed as a connection tree if hierarchically designed)
Right click on the primitive you want to constrain and select Locate ⇒ Locate in Assignment Editor
Assignment Editor will start, so set arbitrary constraints from the Assignment Name field