Set as follows in the Assignment Editor.
・To : Corresponding pin name
・Assignment Name: D* Delay (I/O buffer to input register)
・Value : *Offset value less than 2
 
*1: * indicates a different number depending on the selected device, input/output, etc.
*2: About the offset value
The delay value of Programmable IOE Delay is set step by step, not absolute value setting.
This is called "offset", and the delay value can be changed by inputting the offset value from the maximum and minimum values of Delay.
It's decided.
 
Take the Stratix III device as an example.
・Maximum/minimum value of Programmable IOE Delay of Stratix III is described in the following document.
　　　　https://www.altera.com/en_US/pdfs/literature/hb/stx3/stx3_siii52001.pdf
Table 1-41. Stratix III IOE Programmable Delay
 
The D1 delay value for the C2 speed grade is
Max: 748ps
Minimum: 0ps
, and the offset value ( Available Settings ) has 16 steps from 0 to 15.
 
If you set the offset value to "7", it will be set to about 374 ps, which is half of the maximum of 748 ps.
 
Whether or not the actual settings have been enabled can be confirmed by the Compilation Report after compilation.
You can check it from [Fitter] - [Resource Section] - [Pad to Core Delay Chain Fanout].