As you are aware, Stratix IV does not support VCCIO = 3.3V.
However, by setting VCCIO = 3.0V, connection with 3.3V-LVTTL and 3.3V-LVCMOS is possible.
 
This is described in the Device Handbook at the URL link below.
It says "The 3.3-V LVTTL/LVCMOS standard is supported using VCCIO at 3.0 V."
Other information is also posted, so please refer to it.

  https://www.altera.com/en_US/pdfs/literature/hb/stratix-iv/stx4_siv51006.pdf
 
For Quartus II settings, use the Assignment Editor or Pin Planner to select 3.3V-LVTTL or 3.3V-LVCMOS for the corresponding pins.

After compiling, if you look at the VCCIO of the bank where the pins registered with 3.3V-LVTTL or 3.3V-LVCMOS are arranged, you can confirm that it is set at 3.0V.