<Warning message>

Message : PLL ”<name>” has settings that may cause the lock circuit to fail due to high compensation variability.
CAUSE: You instantiated a PLL with settings that may cause the lock circuit to fail due to high compensation variability.
ACTION: To avoid getting this warning, disconnect the lock circuit or increase the bandwidth for the specified PLL (for example, use medium or high bandwidth).
Otherwise, contact Altera Applications for assistance.

This Critical Warning indicates that the Lock signal used by the ALTPLL function may come off during operation.
This message may be displayed depending on the setting value on the designer's side.
 
As a solution,
1) When designing a PLL on the Megawizard Plug-In Manager GUI, there is a bandwidth setting.
Change the value of and recompile.
2) If you do not need to carefully monitor the phase relationship between the input and output clocks of the PLL, the Lock signal should be
Set not to use.
(Even if the PLL is out of lock, it does not mean that the output Jitter is bad and there is a problem with the quality.
not)