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Intel: How should TimeQuest define signals that do not require timing analysis, such as asynchronous signals and test circuits?
For paths in your design that do not require timing analysis, you can specify false paths in your design (that is, paths that can be ignored during timing analysis) using the "set_false_path" command.
See the Quartus II Help below for how to write commands.
http://quartushelp.altera.com/14.1/master.htm#mergedProjects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_set_false_path.htm
In addition, please refer to the following materials as well.
"TimeQuest ~ How to give timing constraints ~"
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