Various Altera FPGA devices enter a power-on reset (POR) state after power-on.
POR occurs before the FPGA device configuration sequence and serves as a wait time for the system power to stabilize.
 
POR time varies by device or configuration.
 
example)
Standard POR (up to 200ms) or Fast POR (up to 9ms) in Cyclone III devices depending on MSEL pin setting
You can select.
 
For Stratix IV devices, up to 300ms for low and up to 12ms for high PORSEL pin polarity
can be selected.
 
For other device series, please refer to the datasheet of each device.
 
 
During the POR period, the nSTATUS pin will be low to indicate a busy state.
The CONF_DONE signal also goes low to indicate an unconfigured state.
 
After the POR period is complete, the nSTATUS pin is released (high by an external pull-up resistor) and configuration begins.