Intel: What is the function of the DEV_CLRn pins?
Category: Specifications
Tools: Quartus® Prime / Quartus® II
device:-
The DEV_CLRn pin is a pin for clearing (resetting) all device registers at once.
Driving this pin low clears all registers regardless of the design.
Note that this clear signal does not use the global line.
If you want to use this pin as a DEV_CLRn pin, you must configure and compile on Quartus® Prime / Quartus® II.
- Select Assignments menu ⇒ Device and click the Device & Pin Options button in the dialog Box.
- Enable the Enable device-wide reset (DEV_CLRn) option in the General tab.
If this pin is not used as a DEV_CLRn pin, it can be used as a regular user I/O pin.
Experienced FAE
Free consultation is available.
From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.