Intel: I wrote default (Verilog-HDL language) and when others (VHDL) in the HDL language state machine description, but it does not work properly. When I checked the operation on the actual machine, I found that it behaves as if it were in an illegal state. Is there a solution?

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Intel: I wrote default (Verilog-HDL language) and when others (VHDL) in the HDL language state machine description, but it doesn't work properly. When I checked the operation on the actual machine, it seems to be in an illegal state. Is there any workaround?

Quartus Prime

Altera's Quartus II software may optimize the default (Verilog-HDL language) and when others (VHDL) descriptions when the state machine is described in HDL.
Therefore, even if these descriptions are made in the design, if the state transitions to an illegal state for some reason, a phenomenon occurs in which it becomes impossible to return.

To avoid this phenomenon, set the Quartus II setting shown below to “On”.

1. Select Assignments ⇒ Settings.
2. Click the Analysis & Synthesis Settings ⇒ More Settings button.
3. Set Safe State Machine to "On".

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