Intel: Is there a way to check the frequency range of the input clock that the PLL can lock?

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Intel: Is there a way to check the frequency range width of the input clock that can be locked by the PLL?

Clock/PLL Quartus Prime

To check the frequency range of the input clock that can be locked by the PLL installed in each FPGA, go to the Quartus II Processing menu ⇒ Compilation Report ⇒ Fitter ⇒ Resource Section ⇒ PLL Summary
You can check from Freq min lock to Freq max lock in the report file by selecting .

Note that Fitter (placement and routing) must be executed in advance.

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