Category: Simulation
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Simulation of Generic Serial Flash Interface (GSFI) Intel® FPGA IP is possible.

The GSFI IP requires a simulation model of the IP itself and a simulation model of the flash ROM connected to the FPGA.
There are two ways to run a simulation that includes the flash ROM simulation model. Please select one of them.

[Method 1] Use the default EPCQ1024 simulation model
To use this method, in the IP parameter editor
Generate a simulation model by turning on the "Simulation tab" > "Enable Simulation" setting.

[Method 2] Manually instantiate the memory model (using a wrapper file)
See AN720 for how to do this.

　
<Reference materials>
AN720: Simulating the ASMI Block in Your Design
Generic Serial Flash Interface Intel® FPGA IP User Guide