Intel: Error(18101): An external memory interface or PHYLite IP core reference clock fed by a cascaded PLL. Connect the external memory interface or PHYLite IP core reference clock to an input buffer

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Intel: Error(18101): An external memory interface or PHYLite IP core reference clock fed by a cascaded PLL. Connect the external memory interface or PHYLite IP core reference clock to an input buffer

Agilex Arria Cyclone IP Quartus Prime Stratix Clock/PLL

Category: Devices
Tools: Quartus® Prime Pro Edition, Lite Edition
Devices: Agilex™, Stratix® 10, Arria® 10, Cyclone® 10 GX

The error occurs because the reference clock for the PHY Lite for Parallel Interfaces Intel® FPGA IP uses the output clock of the PLL.
It is recommended to input the reference clock from a dedicated pin for better signal quality.

[PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide]
* See the "Reference Clock" section in each device family chapter.

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