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Intel: For functional safety, we expect to implement as safe as needed for each instance within an Intel FPGA design. When using Nios® II Debugging is done using JTAG, is it better to put the JTAG module on the safe side?
Category: Nios® II
tool: -
device:-
Although it depends on the design concept, it seems that debugging functions are generally implemented on the non-safe side in many cases.
When debugging Nios® II via JTAG,
You should separate the JTAG_UART component in Platform Designer from the Nios® II JTAG Debug Module.
If you use the JTAG_UART component to debug your system over JTAG, implement JTAG_UART on the non-secure side.
The Nios® II JTAG debug module, on the other hand, is embedded within the Nios® II Processor Core and encrypted as IP to handle processor debugging.
Therefore, it is not possible to implement only this JTAG debug module on the non-secure side.
(Implemented on the safe side as a Nios® II core.)
For information on how to safely implement each instance in the FPGA design as a Safety IP, see
Please refer to the document below.
AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
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