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Intel: I created a memory IP (ROM/RAM) in IP Catalog or Platform Designer and registered the initial values, but the initial values are not reflected in the RTL simulation results.
Category: Simulation
Tools: Questa*, ModelSim* (both include Intel® FPGA Edition)
device:-
Specify the *absolute path* for the initial value file (.mif/.hex) in the parameters when creating the memory IP.
If the initial value file is registered with a relative path, it will not be reflected in the simulation results.
A warning or error message is displayed.
<Message example when creating IP in Verilog HDL>
# ** Warning: (vsim-3534) Failed to open file "../<file_name>.hex" for reading.
# No such file or directory. (errno = ENOENT)
# ERROR: cannot read ../<file_name>.hex.
To specify the initial value file with an absolute path, specify it on the IP parameter setting screen as shown in the figure below.
or
When editing and specifying the generated *.vhd or *.v, change the relative path of *.mif or *.hex described on the right side of the parameter name below to an absolute path.
| IP generation language | parameter name |
|
VHDL |
init_file => ".mif or .hex file path" |
|
Verilog HDL |
altsyncram_component.init_file = ".mif or .hex file path" |
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