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Intel: How do I manually specify the location of the PLL Intel FPGA IP?
Category: Devices
Tools: Quartus® Prime Standard Edition, Quartus® Prime Lite Edition
Devices: Stratix® V, Arria® V, Cyclone® V
To manually locate the PLL Intel FPGA IP, use the Assignment Editor.
|
To column |
Node Names for PLL Intel FPGA IP |
|
Assignment Name field |
Location |
|
Value column |
Location information to be placed |
The selected node name differs depending on the Element name selected in the Value field.
Please refer to the table below and set the location of the PLL with one of the constraints.
|
recommendation |
Node selected in the To field |
Element name selected in the Value field |
Alignment specified in the Value field |
||
|
X |
Y |
Z |
|||
|
★ |
*|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL |
Fractional PLL |
Specify a number that can be found in PLL Locations in the Device Handbook |
Specify a number that can be found in PLL Locations in the Device Handbook |
0 |
|
*|altera_pll:altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT |
PLL Reference Clock Select Block |
Specify a number that can be found in PLL Locations in the Device Handbook |
Need to check with Chip Planner etc. |
0 |
|
|
*|altera_pll:altera_pll_i|general[0].gpll~PLL_RECONFIG |
PLL Reconfiguration Block |
Specify a number that can be found in PLL Locations in the Device Handbook |
Need to check with Chip Planner etc. |
0 |
|
In addition to searching with the Assignment Editor's Node Finder, there is another way to specify the PLL node name, which is to temporarily perform fitting, select the node name from the compile report, and specify the location in the Assignment Editor. . (Refer to the figure below)
Note that the V-series FPGA's built-in PLL has a correlation between the layout of the PLL reference clock pin and the location of the PLL (see figure below). Due to the structure of the device, it cannot be placed in a PLL that is not connected to a clock pin even if a location is specified.
Example: Arria® V GX B5 and B7 Devices, and Arria® V GT D7 Device PLL Locations
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