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Intel: An AXI ID Bus error occurs when using AXI in Platform Designer. error: arria10_hps_f2sdram0_data: width of slave id signals (4) must be atleast 5. increase slave id width or reduce widths for any connected axi master
Category: Platform Designer
Tools: Quartus Prime
Device:-
AXI ID width can be adjusted by inserting AXI Bridge between Master and Slave.
It is described to avoid by inserting AXI Bridge in the following Intel community.
https://community.intel.com/t5/Programmable-Devices/Width-of-Slave-id-4-must-be-min-5-Increase-slave-ID-width-or/td-p/240175
Details of AXI Bridge are described in the following document.
[Intel® Quartus® Prime Standard Edition User Guide Platform Designer] 4.1.6. AXI Bridge
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-platform-designer.pdf#page=219
Platform Designer's internal buses do not auto-adjust.
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