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Intel: Is it possible to control the flow of received data even if the Triple Speed Ethernet IP does not implement FIFO (Use internal FIFO is not set)?
Category: Triple Speed Ethernet
tool: -
Device:-
For configurations without FIFO, back pressure is applied on the receive path (Avalon-ST) with the upper side.
Since it is not supported, if the upper side is not ready to receive data,
The received data will be discarded.
(You can find the following statement by searching for Frame Writing.)
MAC variations without internal FIFO buffers do not support backpressure on the Avalon-ST receive interface.
In this variation, if the receiving component is not ready to receive data from the MAC function,
the frame gets truncated with error and subsequent frames are also dropped with error.
By sending a pause frame to the transfer source via the transmission path, data transmission is stopped for a certain period of time, so
Provides flow control.
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