Categories: -
Tools: Quartus® Prime
Device: Cyclone® IV E

Terasic's DE0-Nano board implements the Cyclone® IV E device family (EP4CE22F17C6N), so this can be achieved by writing the following instance in your design:

■ Verilog HDL description example

cycloneive_crcblock u0
(
.clk (clk), // ED_CLK clock source
.shiftnld (1'b0), // ED_SHIFTNLD source
.ldsrc (1'b0), // LDSRC source
.crcerror (crcerror_core_out), // CRCERROR_CORE out destination
.regout ()
);