Intel: Even if I change the reference clock input of Stratix® 10 GX PHYLite IP after the FPGA configuration is complete, is there no problem if I reset the PHYLite IP?

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Intel: If I change the reference clock input of the Stratix® 10 GX PHYLite IP after the FPGA configuration is complete, does it matter if I reset the PHYLite IP?

Stratix external memory

Category: Memory Interface
Tools: Quartus® Prime Pro Edition
Device: Stratix® 10

Yes, in the case of PHYLite IP, there is no problem if you reset it.

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