Intel: Assigning a single-ended output clock signal generated in Zero Delay Buffer mode of the ALTPLL IP to the device's PLL output dedicated pin PLL_L_CLKOUTn (suffix n) results in a compilation error; assigning it to PLL_L_CLKOUTp (suffix p) resolves the error. it was done. why?

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Intel: Assigning a single-ended output clock signal generated in Zero Delay Buffer mode of the ALTPLL IP to the device's dedicated PLL output pin PLL_L_CLKOUTn (end n ) results in a compilation error, and assigning it to PLL_L_CLKOUTp (end p ) corrects the error. it was done. why?

IP Quartus Prime

Category: IP (Other)
Tools: Quartus® Prime
device:-

Single-ended output clock signals are only supported on the PLL_L_CLKOUTp (suffixed with p ) pins.
Therefore, when using in Zero Delay Buffer mode, assign the output signal to the dedicated PLL pin marked with a p at the end instead of an n at the end.

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