Intel: When I tried to simulate the PLL, there was a slight difference in the frequency of the output clock between the RTL simulation file *.v and the gate level simulation file *.vo. Why is this?

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Intel: When I tried to simulate a PLL, there was a slight difference in the output clock frequency between the *.v file for RTL simulation and the *.vo file for gate level simulation. why is this?

simulation

Category: Simulation
Tools: ModelSim®
Device: All

The actual frequency value set for the PLL is the Actual Settings such as Output Clocks→clk c0 displayed in the PLL configuration wizard.
If there is a difference between the set frequency and the actually set frequency (Actual Setting), there will be a difference in the output clock frequency between *.v and *.vo.

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