Intel: If I use the Modular ADC core Intel FPGA IP alone and not within Platform Designer, is the reset input signal an asynchronous reset? How long is the reset period required?

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Intel: When using the Modular ADC core Intel FPGA IP alone and not in Platform Designer, is the reset input signal an asynchronous reset? How long should the reset period be?

IP MAX

Category: IP (Other)
tool:-
Device: MAX®10

Designed with asynchronous reset and no reset period constraint.

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