Intel: In designs using MAX® 10 PLLs, a non-clock signal pll_lock_sync was reported in the Timing Analysis Unconstrained Paths => Clock Status Summary. This signal is the PLL Locked signal, but why was it recognized as a clock?

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Intel: Non-clock signal pll_lock_sync was reported in Unconstrained Paths => Clock Status Summary in Timing Analysis for designs with MAX® 10 PLLs. This signal is the Locked signal of the PLL, but why was it recognized as a clock?

MAX Quartus Prime Timing Constraints/Analysis

Category: Timing Constraint/Analysis
Tools: Quartus® Prime
Device: MAX®10

It seems that the Timing Analyzer recognizes it as a clock by connecting the Locked signal of the PLL to the clock pin of the FF.
In this case, constraints that do not allow analysis, such as set_false_path, are invalid, so the design must be changed so that it is not connected to the FF clock.

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