Category: IP (Other)
Tools: Quartus® Prime
device:-

Ensure that the input clocks (rx_inclock/tx_inclock) for ALTLVDS_RX and ALTLVDS_TX are from the same clock source.
Even if the parameters of the internal counters of each PLL are the same, they will not be shared if the input clocks are driven by different sources.

This information is also included in the user manual.
For PLL merging to happen, the input clocks and the settings on the outputs must be specific.

LVDS SERDES Transmitter / ReceiverIP Cores User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altlvds.pdf
(Resource Utilization and Performance section)

If the LVDS PLL sharing is successful, the following message will be displayed in the compilation report:

ID:176132 Successfully merged PLL <name> and PLL <name>