Intel: When performing Arria® 10 I/O PLL Reconfiguration, register settings are made for the PLL Reconfig Intel FPGA IP, but the values written to the registers are not written correctly. Why?

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Intel: When I perform Arria® 10 I/O PLL Reconfiguration, I set the register settings for the PLL Reconfig Intel FPGA IP, but the values I write to the registers are not written correctly. Why?

Arria configuration/programming

Category: Configuration/Programming
tool:-
Device: Arria® 10

A stable external clock (free running clock) must be supplied using mgmt_clk for the clock when accessing the registers of the PLL Reconfig Intel FPGA IP.
For details, please refer to the following documents.

AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an728.pdf

(Design Considerations > Other Design Considerations)

I/O PLL reconfiguration interface supports a free running mgmt_clk signal.

Taken from <<AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices>>

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