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Intel: Is it possible to handle FPGA internal pull-ups for Cyclone® V LVDS pins?
Category: Specifications
Tools: Quartus® Prime
Device: Cyclone® V
It is possible to set a weak pull up resistor in the Quartus® Prime settings, but it cannot be used if the IO standard for that pin is LVDS.
Please refer to the following document for the setting method.
https://www.macnica.co.jp/business/semiconductor/articles/ELS1413_Q1510_21__1.pdf
(3. Internal pull-up setting <Weak Pull-Up Resistor> item)
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