Category: PCI-Express
tool:-
Device: Arria® 10

Must be stable before deasserting PERST# (pin_perst).
In the case of CvP, the IO image is programmed first, then the Linkup sequence is performed after PERST# is released.
Refclk to the device should be stably input before this PERST# is released.

Please also refer to the following Knowledge Base.

When using the Intel Arria 10 PCIe* Hard IP in CvP or Autonomous mode, can the PLLs or transceivers be recalibrated in user mode if the reference clock is not stable during power up.
https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2020/when-using-the-intel--arria--10- pcie--hard-ip-in-cvp-or-autonomo.html