Intel: How to access Slave inside Platform Designer from external CPU using SPI Slave to Avalon Master Bridge Core?

Quartus Prime Platform Designer

Category: Platform Designer
Tools: Quartus® Prime
device:-

Please implement it referring to the sample below.

SPI Slave to Avalon Master Bridge Design Example
https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-spi-bridge.html?elq_cid= 5331786_ts1605579456607&erpm_id=8281062_ts1605579456607

For details of the protocol, please refer to the following documents.
(Reference) Embedded Peripherals IP User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf
(See Section 6. SPI Slave/JTAG to Avalon Master Bridge Cores)

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