Category: SoCs
Tool: SoC EDS
Device: Cyclone® V

<Command>
SOCFPGA_CYCLONE5 # mdio list
mii0:

U-Boot defaults to EMAC1 as shown below.

C:\intelFPGA\18.1\embedded\examples\hardware\cv_soc_devkit_ghrd\software\preloader\generated\pinmux_config.h

#define CONFIG_HPS_EMAC0 (0) #define CONFIG_HPS_EMAC1 (1) #define CONFIG_HPS_USB0 (0) #define CONFIG_HPS_USB1 (1) #define CONFIG_HPS_NAND (0) #define CONFIG_HPS_SDMMC (1) #define CONFIG_HPS_QSPI (1) #define CONFIG_HPS_UART0 (1) #define CONFIG_HPS_UART1 (0) #define CONFIG_HPS_TRACE (1) #define CONFIG_HPS_I2C0 (1) #define CONFIG_HPS_I2C1 (0) #define CONFIG_HPS_I2C2 (0) #define CONFIG_HPS_I2C3 (0) #define CONFIG_HPS_SPIM0 (1) #define CONFIG_HPS_SPIM1 (0) #define CONFIG_HPS_SPIS0 (0) #define CONFIG_HPS_SPIS1 (0) #define CONFIG_HPS_CAN0 (1) #define CONFIG_HPS_CAN1 (0)

C:\intelFPGA\18.1\embedded\examples\hardware\cv_soc_devkit_ghrd\software\preloader\uboot-socfpga\include\configs\socfpga_common.h

/* * network support */ #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_DESIGNWARE_ETH 1 #endif #ifdef CONFIG_DESIGNWARE_ETH #define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS #define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS /* console support for network / #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_CMD_PING / designware / #define CONFIG_NET_MULTI #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_DW_SEARCH_PHY #define CONFIG_MII #define CONFIG_PHY_GIGE #define CONFIG_DW_AUTONEG #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) #define CONFIG_PHYLIB #define CONFIG_PHY_MICREL #define CONFIG_PHY_MICREL_KSZ9021 / phy / #define CONFIG_EPHY0_PHY_ADDR 0 #define CONFIG_EPHY1_PHY_ADDR 4 #define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" #define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 #define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" #define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 / Type of PHY available / #define SOCFPGA_PHYSEL_ENUM_GMII 0x0 #define SOCFPGA_PHYSEL_ENUM_MII 0x1 #define SOCFPGA_PHYSEL_ENUM_RGMII 0x2 #define SOCFPGA_PHYSEL_ENUM_RMII 0x3 #endif / CONFIG_DESIGNWARE_ETH */

C:\intelFPGA\18.1\embedded\examples\hardware\cv_soc_devkit_ghrd\software\preloader\uboot-socfpga\include\configs\socfpga_cyclone5.h

/* EMAC controller and PHY used */ #define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE #define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR #define CONFIG_PHY_INTERFACE_MODE SOCFPGA_PHYSEL_ENUM_RGMII