Intel: There is a specification of tCS min (CS# High Time (Read Instructions), CS# High Time (Program/Erase)) on the QSPI Flash side, but there was no such timing regulation on the Cyclone® V SoC side. How should I meet it?

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Intel: There is a specification of tCS min (CS# High Time (Read Instructions), CS# High Time (Program/Erase)) on the QSPI Flash side, but there was no timing regulation on the Cyclone® V SoC side. how should i fill it?

SoC FPGAs

Category: SoCs
tool:-
Device: Cyclone® V

The QSPI controller is designed so that multiple commands cannot be set and executed at once.
Therefore, there are no regulations for SoC devices, and it is necessary to take care with software in order to comply with the regulations on the QSPI Flash side.

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