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Intel: In Cyclone® V SoC, I'm trying to route the HPS's SPI master device to the FPGA, but sclk is missing.
Category: SoCs
Tools: Quartus® Prime
Device: Cyclone® V
If the pins of the SPI master device (spim) implemented in the Hard Processor System (HPS) are routed to the FPGA side,
sclk appears as a separate port.
Platform Designer (formerly known as Qsys) filters may not show the spim_sclk_out port.
(For example, it will not appear if the Hide Clocks and Resets filter is selected.)
In this case, try All Interfaces as the Filter type.
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