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Intel: In Arria® V SoC, trying to route HPS SPI master device to FPGA but no sclk.
Category: SoCs
Tools: Quartus® Prime
Device: Arria® V
If you route the pins of the SPI master device (spim) implemented in the Hard Processor System (HPS) to the FPGA side,
sclk appears as a separate port.
The spim_sclk_out port may not be visible due to the filtering capabilities of Platform Designer (formerly known as Qsys).
(For example, it will not appear if the Hide Clocks and Resets filter is selected.)
In this case, set the Filter type to All Interfaces and check.
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