Intel: "FPGA I/O Timing Parameters" is shown in the "SDRAM Controller Core" section of the "Embedded Peripherals IP User Guide". This is the setting when tCLK is 20ns, but what are the values of other timing parameters when tCLK is different?

Narrow down by specifying conditions

There are currently 4292 hits.

Intel: "FPGA I/O Timing Parameters" is given in the "SDRAM Controller Core" section of the "Embedded Peripherals IP User Guide". Here is the setting for tCLK = 20ns, but what are the other timing parameters for different tCLK values?

Quartus Prime external memory

Category: External memory interface
Tools: Quartus® Prime
device:-

Embedded Peripherals IP User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf

"FPGA I/O Timing Parameters" requires the following four timing parameters in addition to tCLK.
1. tCO_MIN
2. tCO_MAX
3. tH_MAX
4. tSH_MAX

Please refer to the following items of TimeQuest and set these values.
tSU/tH/tCO : See TimeQuest Report Datasheet
MAX : Set Operating Condition to 6_slow_1100mv_85c
MIN : Set Operating Condition to MIN_fast_1100mv_0c

Specifically, it will be as follows.
1. tCO_MIN
Set Operating Condition to MIN_fast_1100mv_0c
=> Adopt the smallest SDRAM signal value in "Minimum Clock to Output Times" from TimeQuest's Report Datasheet

2. tCO_MAX
Set Operating Condition to 6_slow_1100mv_85c
=> Adopt the largest SDRAM signal value in "Clock to Output Times" from TimeQuest's Report Datasheet

3. tH_MAX
Set Operating Condition to 6_slow_1100mv_85c
=> Adopt the largest SDRAM signal value in "Hold Times" from TimeQuest's Report Datasheet

4. tSH_MAX
Set Operating Condition to 6_slow_1100mv_85c
=> Adopt the largest SDRAM signal value in "Setup Times" from TimeQuest's Report Datasheet

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form