Intel: When using EMIF (External Memory Interface) IP with Arria® 10 or later devices, is it necessary to set the I/O Standard for the external pins for EMIF (DQ, DQS, Add/Cmd, etc.) in the Assignment Editor?

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Intel: When using EMIF (External Memory Interface) IP in Arria® 10 or later devices, it is necessary to set I/O Standard in Assignment Editor for external pins for EMIF (DQ, DQS, Add/Cmd, etc.) mosquito?

Arria Quartus Prime External Memory

Category: External memory
Tools: Quartus® Prime
Device: Arria® 10

No, you don't.
The Arria® 10 EMIF IP does not require the I/O Standard to be set in the Assignment Edition, it is set in the "FPGA I/O" tab of the EMIF's IP Parameter Editor.
This setting is reflected in the EMIF IP file and the setting is applied at compile time.

Target FPGA : Arria® 10, Cyclone® 10 GX, Stratix® 10, Agilex™

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