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Intel: The following warning about PLL occurs in the Quartus® Prime Fitter. Please tell me the measures.
Category: Quartus® Prime
Tools: Quartus® Prime
Device: Cyclone® V
<Warning message>
Warning (177007): PLL placed in location FRACTIONALPLL_Xx_Yx_Nx do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
Add a “Match PLL Compensation Clock” constraint to the divclk of the target PLL in the Assignment Editor.
Please refer to the Knowledge Badabase below.
（参考）
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd05232014_921.html
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd10232014_332.html
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