Category: PCI-Express
Tools: Quartus® Prime / ModelSim®
Device: Arria® 10

Please refer to the following user guide for the simulation procedure.

(Reference) Intel Arria 10 and Intel Cyclone 10 GX Avalon Memory Mapped (Avalon-MM) Interface for PCI Express User Guide
https://www.intel.com/content/www/us/en/programmable/documentation/lbl1415230609011.html#qne1525826942977
(14. Avalon-MM Testbench and Design Example for Root Port)

The point in the procedure is to enable BAR0 (64-bit) or BAR0 & 1 (32-bit) in the Base Address Registers tab of IP Settings.
If this is not done, the TXS and CRA Ports of the generated simulation model will be unconnected and the simulation will not proceed correctly.

In the Base Address Registers tab, only enable BAR0, or BAR0 and BAR1. All other BARs are disabled in the current Root Port design example.
If you set BAR0 to use 64-bit prefetchable memory, you need to disable BAR1.
If you set BAR0 to use 32-bit prefetchable memory or 32-bit non-prefetchable memory, you can enable or disable BAR1

Excerpt from <<14.1.1. Example Design Generation>>

Then follow the steps in 14.2.1. Simulating the Design Example with the generated model.

It has been confirmed that it runs normally on the following simulators.

- ModelSim® SE-64 2019.1
- ModelSim®-Intel® FPGA Edition 10.6d (including Starter Edition)

(supplement)
In the Windows OS environment, it may not be completed normally due to the file path length limit, so please do it in the Linux environment.