Category: Development Kit / Transceiver
Tools: Quartus® Prime
Device: Stratix® 10

<Example Design>
stratix10TX_1st280yf55_si_revB_v18.1.2b277_v1.0\examples\qts_pam4_com\qts_pam4_com\pam4_xcvr_com.qpf

<Error message example>
Error (13305): Verilog HDL error at pam4_xcvr_com.v(130): can't find port "rsfec_avmm2_avmmread_in" File: D:/intelFPGA_pro/Project/stratix10TX_1st280yf55_si_revB_v18.1.2b277_v1.0/examples/qts_pam4_com/parm4_com4_1_com/parm4_xcv.1 pam4_xcvr_com.v Line: 130
Info (16867): Verilog HDL info at nphy.v(6): nphy is declared here File: D:/intelFPGA_pro/Project/stratix10TX_1st280yf55_si_revB_v18.1.2b277_v1.0/examples/qts_pam4_com/pam4_xcvr_com_19.3/qts_pam4_com/nphy/synth nphy.v Line: 6

Please comment out the following because the design of the top layer of the design still has the port that was in the past version E-Tile nativePHY.

.rsfec_avmm2_avmmread_in ( ), // input, width = 1, RSFEC_avmm2.read .rsfec_avmm2_avmmrequest_in ( ), // input, width = 1, .waitrequest .rsfec_avmm2_avmmwrite_in ( ), // input, width = 1, .write

Regarding the IO Standard of pll_refclk0 and pll_refclk1, compilation was passed even with LVDS in the past version, but if it does not pass depending on the version, please change to Differential LVPECL.