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Intel: Configure QDR II SRAM with Arria® 10. Can the Address/Command pins be placed freely at this time?
Category: External memory interface
tool:-
Device: Arria® 10
No, the QDR II SRAM Address/Command pins will be fixed.
For Arria® 10, the pinout for the External Memory Interface is as shown in the document below.
(Reference) External Memory Interface Pin Information for Intel Arria 10 Devices
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-10/arria10emif.pdf
"QDRII/II+Scheme 1" in this document applies, but the pin placement is determined for the IO BANK where the Address/Command pin can be placed.
This is also true for Stratix® 10.
(Reference) External Memory Interface Pin Information for Intel Stratix 10 Devices
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/stratix-10/stratix10emif.pdf
* Cyclone® 10 GX is not supported as it does not support QDR II SRAM.
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