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Intel: Is it possible to use the IP provided by Quartus® Prime as-is for creating OpenCL™ kernels?
Category: OpenCL™
Tools: Intel® FPGA SDK for OpenCL™
device:-
It is possible, but basically difficult due to some constraints.
The restrictions are summarized below.
Intel FPGA SDK for OpenCL Pro Edition: Programming Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl_programming_guide.pdf
(search for Restrictions and Limitations in RTL Support for the Intel FPGA SDK for OpenCL Library Feature)
Among them, there is a restriction that the I/F is Avalon ST, but most of the prepared IPs are Avalon MM, so it is difficult to actually specify the specifications.
An RTL module must use a single input Avalon-ST interface.
That is, a single pair of ready and valid logic must control all the inputs.
In addition, there are restrictions such as matching the input/output data width to the kernel and not being able to connect between libraries, so please pay close attention to these restrictions when considering using it.
RTL modules cannot connect to external I/O signals.
All input and output signals must come from an OpenCL kernel.
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