Intel: How do I change the baud rate setting while the Preloader is running for the Cyclone® V SoC's Hard Processor System (HPS) UART?

Cyclone SoC EDS/DS-5 SoC FPGAs

Category: SoCs
Tool: SoC EDS
Device: Cyclone® V

The baud rate that Preloader initially applies is defined in the following file under the Preloader/U-Boot source tree.

Filename: uboot-socfpga\include\configs\socfpga_common.h

00346|/* 00347| * NS16550 Configuration 00348| / 00349|#define CONFIG_SYS_NS16550 00350|#ifdef CONFIG_SYS_NS16550 00351|#define UART0_BASE SOCFPGA_UART0_ADDRESS 00352|#define CONFIG_SYS_NS16550_SERIAL 00353|#define CONFIG_SYS_NS16550_REG_SIZE -4 00354|#define CONFIG_CONS_INDEX 1 00355|#define CONFIG_SYS_NS16550_COM1 UART0_BASE 00356|#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} 00357|#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 00358|#define CONFIG_SYS_NS16550_CLK 1000000 00359|#else 00360|#define CONFIG_SYS_NS16550_CLK (cm_l4_sp_clock) 00361|#endif 00362|#define CONFIG_BAUDRATE 115200 00363|#endif / CONFIG_SYS_NS16550 */

Since it does not support bsp-editor option specification, it is necessary to rewrite the definition in the source code.

The initial setting should be set to 9600 by changing line 362 of the above source as follows.
#define CONFIG_BAUDRATE 115200

#define CONFIG_BAUDRATE 9600

 

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