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Intel: Added the Intel HLS Compiler generated IP to the Platform Designer system and generated a simulation model (VHDL). When simulating with ModelSim, my IP outputs indeterminate values.
Category: HLS
Tools: Quartus® Prime / Intel® HLS Compiler
Device: Cyclone® V
Tool used: Quartus® Prime Standard Edition v17.1
ModelSim®-SE
If you change the simulation model to VHDL when generating with Platform Designer, the module name of the component generated by HLS is incorrect in the automatically generated Platform Designer simulation top hierarchy (inside the simulation folder) and connection is not possible.
It can be avoided by one of the following methods.
(1) Correction of simulation top layer module
Since the component is <component name>_<component name>_internal, modify it to <component name>_internal
(2) Generate simulation model in Verilog
No problem when generated in Verilog
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